jm + cpu   12

ctop
Top for containers (ie Docker)
docker  containers  top  ops  go  monitoring  cpu 
6 weeks ago by jm
Memory Layouts for Binary Search
Key takeaway:
Nearly uni­ver­sally, B-trees win when the data gets big enough.
caches  cpu  performance  optimization  memory  binary-search  b-trees  algorithms  search  memory-layout 
may 2015 by jm
Asus trackpad driver sets the CPU speed to maximum during scrolling
LOL, hardware people writing drivers. Good reason not to buy Asus, I guess
asus  fail  hardware  drivers  throttling  cpu  touchpad  trackpad  scrolling  laptops 
november 2014 by jm
New Low Cost EC2 Instances with Burstable Performance
Oh, very neat. New micro, small, and medium-class instances with burstable CPU scaling:
The T2 instances are built around a processing allocation model that provides you a generous, assured baseline amount of processing power coupled with the ability to automatically and transparently scale up to a full core when you need more compute power. Your ability to burst is based on the concept of "CPU Credits" that you accumulate during quiet periods and spend when things get busy. You can provision an instance of modest size and cost and still have more than adequate compute power in reserve to handle peak demands for compute power.
ec2  aws  hosting  cpu  scaling  burst  load  instances 
july 2014 by jm
examining the Hardware Performance Counters
using the overseer library and libpfm, it's possible for a JVM app to record metrics about L2/DRAM cache hit rates and latency
metrics  hpc  libpfm  java  jvm  via:normanmaurer  l2  dram  llc  cpu 
december 2013 by jm
'Mythbusting Modern Hardware to gain "Mechanical Sympathy"' [slides]
Martin Thompson's latest talk -- taking a few common concepts about modern hardware performance and debunking/confirming them, mythbusters-style
mythbusters  hardware  mechanical-sympathy  martin-thompson  java  performance  cpu  disks  ssd 
may 2013 by jm
Java tip: How to get CPU, system, and user time for benchmarking
a neat MXBean trick to get per-thread CPU usage in a running JVM (via Tatu Saloranta)
java  jvm  monitoring  cpu  metrics  threads 
november 2012 by jm
How to make a security geek feel very old: #Factorisation, #DKIM and @DrZacharyHarris
“A 384-bit key I can factor on my laptop in 24 hours. The 512-bit keys I can factor in about 72 hours using Amazon Web Services for $75. And I did do a number of those. Then there are the 768-bit keys. Those are not factorable by a normal person like me with my resources alone. But the government of Iran probably could, or a large group with sufficient computing resources could pull it off.”

Remember when we thought 512-bit keys would be enough? how time flies!

Of course, John Aycock raised this problem back in 2007, although he assumed it'd take a 100,000-host botnet to crack them (in 153 minutes).
factorisation  moores-law  cpu  speed  dkim  domain-keys  512-bit  cracking  security  via:alec-muffet 
october 2012 by jm
experimental CPU-cache-aware hash table implementations in Cloudera's Impala
via Todd Lipcon -- https://twitter.com/tlipcon/status/261113382642532352

'another cool piece of cloudera impala source: cpu-cache-aware hash table implementations by @jackowayed'. 'L1-sized hash table that hopes to use cache well. Each bucket is a chunk list of tuples. Each chunk is a cache line.'
hashing  hash-tables  data-structures  performance  c++  l1  cache  cpu 
october 2012 by jm
Bunnie Huang on the simulated 6502
'It makes my head spin to think that the CPU from the first real computer I used, the Apple II, is now simulateable at the mask level as a browser plug-in. Nothing to install, and it’s Open-licensed. How far we have come…a little more than a decade ago, completing a project like this would have resulted in a couple PhDs being awarded, or regarded as trade secret by some big EDA vendor. This is just unreal…but very cool!'
simulation  bunnie-huang  6502  cpu  chips  emulation  hardware  from delicious
september 2010 by jm
www.Visual6502.org
'working from a single 6502, we exposed the silicon die, photographed its surface at high resolution and also photographed its substrate. Using these two highly detailed aligned photographs, we created vector polygon models of each of the chip's physical components - about 20,000 of them in total for the 6502. These components form circuits in a few simple ways according to how they contact each other, so by intersecting our polygons, we were able to create a complete digital model and transistor-level simulation of the chip. This model is very accurate and can run classic 6502 programs, including Atari games. By rendering our polygons with colors corresponding to their 'high' or 'low' logic state, we can show, visually, exactly how the chip operates: how it reads data and instructions from memory, how its registers and internal busses operate, and how toggling a single input pin (the 'clock') on and off drives the entire chip to step through a program and get things done.' Awesome
6502  emulation  physics  simulation  mos  atari-2600  pet  commodore  c-64  cpu  silicon  from delicious
september 2010 by jm
Sort vs. Hash Revisited: Fast Join Implementation on Modern Multi-Core CPUs [PDF]
sort-and-merge is likely to be faster on future SIMD-capable multicore CPUs RSN
sort  merge  hash  join  databases  performance  cpu  simd  multicore  from delicious
june 2010 by jm

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